Bi-Monthly Newsletter - December 2019
UPCOMING EVENTS SONiC & SAI 2019 HIGHLIGHTS


2020 OCP Global Summit

4-5 March, 2020

San Jose Convention Center


Pre-Summit Workshop & Hackathon

2-3 March, 2020

Await for more details

It has been an amazing year 2019 for SONiC ! Thanks to the community for the excellent achievement of 2 releases in this year with 27 new features, 2480 closed pull requests from 200+ active contributors !

It has been a great achievement in standardizing the & as part of SAI !

Successfully hosted & participated in 1 hackathon, 4 workshops & 2 OCP summits and exhibited SONiC capabilities to the world !

Created 7 workgroups to have a focused feature specific community discussions and contributions !

Looking forward for another successful year 2020 !

SONiC COMMUNITY NEWS

Cisco announced supporting of SONiC and SAI on Silicon One and 8000 Series, a high density 400GE new platform for hyperscale providers. For details

Mellanox describes its full support for SONiC as "ASIC to protocol" that includes the service calls, troubleshooting and bug fixes for customers. For details

SONiC RELEASE UPDATES

SONiC release branch 201911 has been created, branch stabilization is in progress.

Features Merged - Build time improvements, Configurable drop counters, Egress mirroring and ACL action support check via SAI, HW resource monitor,L3 perf enhancement, Log analyzer to pytest, Management Framework, Management VRF, Platform test, sFlow, SSD diagnostic tolling and Sub-port support have been merged.
Pending Features - MLAG,VRF and ZTP.

For current status of all features

NEW PLATFORMS
SONiC DESIGN DISCUSSIONS
  • Arista
    7280CR3K-32P4
  • DellEMC
    z9332f-32x400G
  • Mellanox
    SN3800-D112C8
05 NOV 2019

   Support for DPKG local caching   

12 NOV 2019

  DPKG Caching Framework - BRCM    

19 NOV 2019

  Thermal control design  

26 NOV 2019

  Release tracking status discussion  '

03 DEC 2019

  Release tracking status     

10 DEC 2019

  Release tracking status discussion 

17 DEC 2019

  PCI-e diag design specification